The present invention relates to managing power consumption in a processor through clock signal gating and control.
Where power consumption in a processing system is of concern, conventional techniques to reduce power consumption and dissipation include causing the processing system to enter into a sleep mode in which processing functions are shut down, operating voltage/current is cut off, and/or clock signals are gated off. With reference to FIG. 1, an existing processing system 10 is illustrated, which may or may not be prior art to the instant invention. The processing system 10 includes a clock control unit 12 and a plurality of branch circuits 14A, 14B, 14C, 14D operable to distribute clock control signaling to various portions of the processing system 10 in accordance with a tree or rake structure. Each branch circuit 14 includes a local clock buffer circuit 16 (only circuit 16A being shown) in order to start or stop a clock signal that is distributed to a local area of the processing system 10 and/or in order to modulate the clock frequency from a high frequency input clock (HFCLK) to a low frequency output clock (LFCLK).
FIG. 2 is a timing diagram that graphically illustrates relationships among the HFCLK signal, the LFCLK signal, and a control (CONT) signal of the processing system 10. The transformation of the HFCLK signal to the LFCLK signal is accomplished within the local clock buffer 16 as a function of the CONT signal issued from the clock control unit 12. The CONT signal is a square-wave signal transitioning at about one-half the frequency of the HFCLK signal. The local clock buffer 16 may include combinational logic (such as a NAND gate) to produce the LFCLK signal from the HFCLK signal and the CONT signal.
As there may be a significant distance between the clock control unit 12 and the local buffers 16, each branch circuit 14 may include multiple flip-flop stages to accommodate signal delays and propagate the CONT signal to all of the local clock buffers 16.
The clock control unit 12 may be employed in the processing system 10 in order to facilitate the gating of the HFCLK signal(s) to the respective local areas of the processing system 10, the distribution of the LFCLK, and to achieve a sleep mode in which the LFCLK signal is shut down. The clock control unit 12 may facilitate entering and exiting the sleep mode by turning the CONT signal OFF (for sleep mode) and ON (for normal mode).
Among the problems with this approach is that the distribution of the CONT signal throughout the processing system 10 requires the use of the multiple flip-flop stages. The many transitions of the flip-flops to propagate the CONT signal results in high power consumption and dissipation within the processing system. Accordingly, there are needs in the art for new solutions to the problem of power reduction in a processing system using clock signal control.